SMLNJ: Intel x86 back end Compiler Controlled Memory

Interchangeable Back Ends for STM Compilers

If transactional memory is to become a mature technology, TM research groups must be able to run each other’s code and to perform apples-to-apples comparisons of implementation alternatives. For C++ on the x86, significant steps in this direction have been made by compilers from Intel, the University of Dresden, and the GNU Project, which aim to accept the same language API and target the same ...

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations' Perspective

Intel Extended Memory 64 Technology (EM64T) and AMD 64-bit architecture (AMD64) are emerging 64-bit x86 architectures that are fully x86 compatible. Compared with the 32-bit x86 architecture, the 64-bit x86 architectures cater some new features to applications. For instance, applications can address 64 bits of virtual memory space, perform operations on 64-bit-wide operands, get access to 16 ge...

An X86 back-end for the HiPE Compiler

lcc.NET: targeting the .NET Common Intermediate Language from Standard C

The core of the Microsoft .NET platform includes a new virtual machine (VM), the Common Intermediate Language, also known as MSIL. Unlike most other VMs, including the Java VM, MSIL is specifically designed to support a wide range of languages. While it is designed primarily for type-safe, objectoriented languages, it also has facilities that support both low-level languages and very high-level...

Automatically Generating Back Ends for a Portable Assembly Language Using Declarative Machine Descriptions

We show how to generate the back end of an optimizing compiler from a formal description of the syntax and semantics of machine instructions. Our generated back ends for x86, ARM, and PowerPC perform as well as their hand-written counterparts. Automatic generation is enabled by two new ideas: a model of machine-level computation that reduces back-end generation to the problem of finding impleme...